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TECHNICAL FIELD OF THE INVENTION

The present invention relates generally to digital electronic circuits, such as those used in general purpose computers and microprocessors and in special purpose machines. More specifically, the present invention relates to electronic circuits which are used in performing arithmetic operations on two's complement binary numbers.

BACKGROUND OF THE INVENTION

Conventional binary arithmetic circuits perform arithmetic operations, particularly subtraction and negation, in an indirect and inefficient manner. Subtraction has been performed by inverting a subtrahend number to form a one's complement of the subtrahend, adding the inverted subtrahend to a minuend number, and then incrementing the addition result. The incrementing of the addition result is typically accomplished by supplying a carry pulse to an adder when a subtraction is performed. A simple negation has been treated as a special subtraction problem with the minuend forced to equal zero.

Thus, the same indirect steps are involved in obtaining a two's complement negation of an incoming number. Often, additional enabling combinatorial logic is required to selectively invert the subtrahend and to selectively apply the carry pulse when a subtraction or negation operation is required and to prevent inversion of the subtrahend and addition of a carry pulse when addition and other arithmetic operations are required.

In many situations, the indirect techniques for performing subtraction and negation operations are undesirable. These indirect techniques often require an undesirably large amount of circuit area or number of components for their implementation. Moreover, these indirect techniques often cause the propagation delay between the time when an incoming number is valid and the time when the subtraction or negation operation results are valid to be undesirably long.

SUMMARY OF THE INVENTION

Accordingly, it is an advantage of the present invention that an improved arithmetic circuit is provided. Another advantage of the present invention is that an arithmetic circuit is provided which may be incorporated in a wide variety of applications, including arithmetic logic units (ALUs) for microprocessors or other computing circuits, add/subtract circuits, subtraction circuits, and negation circuits.

Another advantage of the present invention is that an arithmetic circuit is provided which generates a two's complement negation of an incoming number in a small amount of space and with a small amount of propagation delay.

Another advantage of the present invention is that an arithmetic circuit is provided which selectively generates a negation of an incoming number.

Another advantage of the present invention is that an arithmetic circuit is provided which selectively performs addition or subtraction operations, wherein the subtraction operations are performed in a direct manner which does not require the generation of a carry input pulse.

Another advantage of the present invention is that an arithmetic circuit is provided which may be adapted to efficiently generate negations for incoming numbers having any number of bits.

Sample Cover Letter:

US'120 Patent Description and Terms

Subject: "Direct Binary Adder/Subtractor"

Dear, President and CEO:

You might find this technology of interest to view. The influence of the chip as the inventor puts it mildly, covers everything from a handheld calculator to a microwave oven. The attached description of software and hardware applications, and NIST's evaluation report will give teaching to those skilled in the art. Selective Negation is the key of just one to the chips configuration to develop software, and can be understood further of the attached description and it's Truth Table. Please send the email address, and to whom I should address in the future for licensing.

Director of Intellectual Property Rights
Attention: Staff Attorney, Patent Suggestion
of New Product Development

Title: Direct Binary Adder/Subtractor
Re: U.S. Patent No. 5,333,120
Law Ref: JRG 93046 UP, 220-2

Description, Licensing Counselors:

The status of the "BINARY TWO'S COMPLEMENT ARITHMETIC CIRCUIT" is patented. That a notice of allowance has been received from the USPTO and issued, U.S. Patent No. 5,333,120 and references cited U.S. PATENT DOCUMENTS.

Over a period of years, I have invented and developed a "Direct Binary Adder/Subtractor." My circuitry enables a microprocessor or other arithmetic circuits to subtract directly. This eliminates the conventional and inefficient two's complement formation operations. My invention uses fewer logical steps to perform subtraction. This produces at least three significant benefits: 1) the silicone process is drastically reduced; 2) the circuitry size is reduced, and most important; 3) the speed of the arithmetic function is dramatically increased.

I believe that my invention is a major breakthrough that will eventually usher in a whole series of important changes in computer technology. This translates into major cost savings and will speed improvements in a wide variety of applications.

My invention is patented. It is my intention to license, sell, or otherwise arrive at a mutually beneficial arrangement concerning my '120 patent rights for the manufacture and sale of the "Direct Binary Adder/Subtractor." I believe that your company's ability to recapture and control sales for a large segment of your industry would undoubtedly be enhanced by having rights to my invention.

If I can provide you with a copy of the '120 honored patent (26 Claims, 6 Drawing Sheets) or any other information regarding my invention, please contact me through the below fast respond e-mail. You may wish to view the '120 patent from the US Patent and Trademark Office Web Site: http://patft.uspto.gov/netahtml/PTO/srchnum.htm

UNITED STATES DEPARTMENT OF COMMERCE

National Institute of Standards and Technology December 02, 1994. Evaluation of the invention entitled "Direct Binary Adder/Subtractor" has been completed. This invention was submitted and evaluation performed according to Section 14 of the Federal Nonnuclear Energy Research and Development Act of 1974.

NIST's Explanation: While your invention technical feasibility describes a novel binary adder that is faster than conventional adders. The speed is achieved by bypassing the need for propagating add carries. Thus, the add carries save the propagation delay time of the carry/borrow character as they progress up the significant digit chain. The speed increase is dramatically noticeable at 64 bits and beyond. Commercial and economic feasibility of the invention, including advantages over competing products or processes on the market or in development.

However, as the patentee has said to conclude the evaluation, the circuitry reduces hundreds of thousands of transistors which does not require the combinatorial logic operations and the results to be undesirably long, this new technology will influence and move the development of (EUV) into the next decade. Those skilled in the art will appreciate and find during their evaluation, that the first adder input signal of all present adders on the market can be permanently grounded. The new subtrahend may be incorporated in this manner until a full-scale adder is developed.

Accordingly, it is an advantage of the present invention that an improved arithmetic circuit is provided. Another advantage of the present invention is that an arithmetic circuit is provided which selectively performs addition or subtraction operations, wherein the subtraction operations are performed in a direct manner which does not require the generation of a carry input pulse.

Conventional binary arithmetic circuits perform arithmetic operations, particularly subtraction and negation, in an indirect and inefficient manner. Present software and hardware are limited to, Sequential Arithmetic. The '120 patent concept of software, hardware, and peripherals of any AI device "Artificial Intelligence" uses a true art of elementary thinking. In other words, neither presence mathematical devices, nor the future next-generation arrival of Merced chip, will be using the processor feature of "Selective Negation."

Selective Negation will ramify present industries DOS obsolete and a means to access the new circuitry direct, in a one-to-one correspondence due to the transition-bit-based technique that the present invention implements. Present software will be utilized until such time the recording software is developed to access further upgraded speed, for the one's complement inefficient manner is selectively eliminated.

Selective Negation will have an ability profound change on the reorganization of industry standards. This impact also reflects the automotive digitized fuel injection, data acquisition, and analysis perception, as we know it today.

These brief descriptions and those skilled in the art will appreciate that the circuitry may be, configured to incorporate any number of industry's needs. These and other changes and modifications, which are obvious to those skilled in the art, are intended to be included within the scope of the present invention.

"BINARY TWO'S COMPLEMENT ARITHMETIC CIRCUIT" REFERENCES CITED U.S. PATENT DOCUMENTS

PRIME: 3,816,734 6/1974 Brendzel...364/786 Ref/Cited 4. Assignee: Bell Telephone Laboratories, Incorporated. Now: AT & T Corporation. USA.
3,437,801:
Frederick A. Wilhelm Jr. Assignee: Electronic Associates Inc. Long Branch NJ.
3,584,206: John T. Evans, Waynesboro VA. Assignee: General Electric Co. NY, NY.
3,631,231: Klaus Lagemann, of Germany. Assignee: U.S. Philips Corporation. NY, NY.
3,699,326: Jerry L. Kindell, Phoenix Arizona. Assignee: Honeywell Info Sys Inc. Waltham MA.

PRIME: 3,975,624 8/1976 Kay...364/786 Ref/Cited 2. Assignee: U.S. of America as represented by the Secretary of the Air Force. Wash, DC. 3,196,262: Kenneth R. Thompson, Roanoke VA. Assignee: General Electric Co. NY, NY.
3,816,734:
Henry Tzvi Brendzel, Parsippany NJ. Assignee: Bell Tele Lab Incorp. BH, NJ.

PRIME: 3,976,866 8/1976 Motegi et al. ...364/786 Ref/Cited 1. Assignee: Fujitsu Ltd. Kawasaki, Japan. Cited: 64-Bit Adder, In IBM Tech Disc, Bull.

PRIME: 4,707,800 11/1987 Montrone et al. ...364/788 Ref/Cited 9. Assignee: Raytheon Co. Lexington, Mass. Missile Sys Div, Electronic Comp Sys Div, Microwave Devices, and Submarine Signal Div, part of their numerous Company's. 3,100,835: Orest J. Bedrij, Poughkeepsie NY. Assignee: IBM Corporation. NY, NY.
3,676,657: Eltje De Boer, Eindhoven Netherlands. Assignee: U.S. Philips Corp. NY, NY.
3,767,906: Richard Lee Pryor, Cherry Hill NJ. Assignee: RCA Corporation. NY, NY.
3,993,891: Gary Randall Beck, of Calif. Assignee: Burroughs Corporation. Detroit Mich.
4,052,604: David S. Maitland, Loveland Colo. Assignee: Hewlett-Packard Co. Palo Alt CA.
4,439,835: David W. Best, of Iowa. Assignee: Rockwell International Corp. El Sgundo CA.
4,523,292: John Armer, Middlesex NJ. Assignee: RCA Corporation. Princeton, NJ.
4,536,855: Steven G. Morton, Oxford Conn. Assignee: Int.-al Tele & Teleg Corp. NY, NY.
4,573,137: Masahide Ohhashi, Sagarnihara Kaisha Japan. Assignee: Tokyo Shibaura Denki, Kaisha Japan.

The Law Offices of Attorney Donald J. Lisa Prior Vice President of Patents Motorola Inc, did represents me in connection with my licensing and enforcement of the above referenced '120 patent. If you are also requesting the terms, conditions, and financial rates under which the patentee is offering a license. To date, Mr. Gilber't has not licensed the '120 patent, and specific terms and conditions and financial rates under which a license would be offered have not yet been determined.

However, as the patentee has said to the industry in general in the many letters he has sent to prospective licensees, his primary interest is in obtaining a one-time, non-refundable, up front, lump sum payment together with per unit royalties on each device made, used, or sold in either software or hardware which is covered by his patent.

He would consider both exclusive and non-exclusive licenses of all or some of his patent rights, field of use licenses, licenses for a term of years or for the life of the patent, or the sale of all or some portion of his 100% ownership interest in the '120 patent.

I am sure you can appreciate that it would involve a great deal of time, money, and effort to determine the present value of my patented invention in view of the numerous possible software and hardware implementations of the invention.

Until I am aware of the specific application of my invention and how it will be used, it would be very difficult to attempt to quantify in vacuo a projected net cash flow pro forma, which would yield the specific financial terms of a license.

We assure you; however, the patentee is only interested in a fair and reasonable return for the use of his invention as guaranteed by the U.S. patent laws generally. Also, you have our promises to work with you in good faith, in a business-like manner, in genuine arms length negotiation to rapidly and as efficiently as possible define the fair value of the patent depending on your actual or prospective use.

We believe the patent offers a significant speed advantage in computer processing. I trust this response is sufficient to enable you to have the patent preliminary evaluated from your company's point of view to determine whether it has any interest in entering licensing discussions with me. If you really need specific terms and conditions and financial rates of a prospective license up front before you can begin evaluating my '120 patent.

I will call my attorney immediately and let him know we would then undertake to develop what seems fair as an opening proposal for general discussion purposes. Thank you for viewing this letter of interest and conducting an evaluation of my invention. Please contact me when you have completed your evaluation.

CONFIRMATION AVAILABLE:
 
I look forward to hearing from you soon.
Kindest personal regards.
 
Sincerely,
JR. Gilber't
Prior President & CEO

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